Data Sheet
REGISTER MAPS
Table 12. Calibration and Power Quality Registers
ADE7816
Register
Bit
Bit Length During
Default
Address
0x4380
0x4381
0x4382
0x4383
0x4384
0x4385
0x4386
0x4387
0x4388
Name
VGAIN
IAGAIN
IBGAIN
ICGAIN
IDGAIN
IEGAIN
IFGAIN
Reserved
DICOEFF
R/W 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Length
24
24
24
24
24
24
24
24
24
Communication 2
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
Type 3
S
S
S
S
S
S
S
S
S
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Description
Voltage gain adjustment.
Current Channel A current gain adjustment.
Current Channel B current gain adjustment.
Current Channel C current gain adjustment.
Current Channel D current gain adjustment.
Current Channel E current gain adjustment.
Current Channel F current gain adjustment.
This register should be ignored.
Register used in the digital integrator algorithm.
When the integrator is enabled, this register
should be set to 0xFFF8000.
0x4389
0x438A
0x438B
0x438C
0x438D
0x438E
0x438F
0x4390
0x4391
0x4392
0x4393
0x4394
0x4395
0x4396
0x4397
0x4398
0x4399
0x439A
0x439B
0x439C
0x439D
0x439E
0x439F
0x43A0
0x43A1
0x43A2
0x43A3
0x43A4
0x43A5
0x43A6
0x43A7
0x43A8
HPFDIS
VRMSOS
IARMSOS
IBRMSOS
ICRMSOS
IDRMSOS
IERMSOS
IFRMSOS
AWGAIN
AWATTOS
BWGAIN
BWATTOS
CWGAIN
CWATTOS
DWGAIN
DWATTOS
EWGAIN
EWATTOS
FWGAIN
FWATTOS
AVARGAIN
AVAROS
BVARGAIN
BVAROS
CVARGAIN
CVAROS
DVARGAIN
DVAROS
EVARGAIN
EVAROS
FVARGAIN
FVAROS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Disables the high-pass filter for all channels.
Voltage rms offset.
Current Channel A current rms offset.
Current Channel B current rms offset.
Current Channel C current rms offset.
Current Channel D current rms offset.
Current Channel E current rms offset.
Current Channel F current rms offset.
Channel A active power gain adjust.
Channel A active power offset adjust.
Channel B active power gain adjust.
Channel B active power offset adjust.
Channel C active power gain adjust.
Channel C active power offset adjust.
Channel D active power gain adjust
Channel D active power offset adjust.
Channel E active power gain adjust.
Channel E active power offset adjust.
Channel F active power gain adjust.
Channel F active power offset adjust.
Channel A reactive power gain adjust.
Channel A reactive power offset adjust.
Channel B reactive power gain adjust.
Channel B reactive power offset adjust.
Channel C reactive power gain adjust.
Channel C reactive power offset adjust.
Channel D reactive power gain adjust.
Channel D reactive power offset adjust.
Channel E reactive power gain adjust.
Channel E reactive power offset adjust.
Channel F reactive power gain adjust.
Channel F reactive power offset adjust.
0x43A9
0x43AA
Reserved
Reserved
This register should be ignored.
This register should be ignored.
0x43AB
WTHR1
R/W
24
32 ZP
U
0x000000
Most significant 24 bits of the WTHR[47:0]
threshold.
0x43AC
WTHR0
R/W
24
32 ZP
U
0x000000
Least significant 24 bits of the WTHR[47:0]
threshold.
Rev. A | Page 37 of 48
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